A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-ch...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2010-11-05T18:54:39Z.
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| Subjects: | |
| Online Access: | Get fulltext |