Photonic Device Layout Within the Foundry CMOS Design Environment
A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
| Main Authors: | , |
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| Other Authors: | , |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2011-03-21T21:17:21Z.
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| Subjects: | |
| Online Access: | Get fulltext |