Photonic Device Layout Within the Foundry CMOS Design Environment

Photonic Device Layout Within the Foundry CMOS Design Environment

A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.

Bibliographic Details
Main Authors: Orcutt, Jason Scott (Contributor), Ram, Rajeev J. (Contributor)
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor), Massachusetts Institute of Technology. Research Laboratory of Electronics (Contributor)
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers, 2011-03-21T21:17:21Z.
Subjects:
Article
Online Access:Get fulltext
Description
Summary:A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
United States. Defense Advanced Research Projects Agency (DARPA)
National Science Foundation (U.S.)

Similar Items