|
|
|
|
LEADER |
01291 am a22002413u 4500 |
001 |
61756 |
042 |
|
|
|a dc
|
100 |
1 |
0 |
|a Orcutt, Jason Scott
|e author
|
100 |
1 |
0 |
|a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
|e contributor
|
100 |
1 |
0 |
|a Massachusetts Institute of Technology. Research Laboratory of Electronics
|e contributor
|
100 |
1 |
0 |
|a Ram, Rajeev J.
|e contributor
|
100 |
1 |
0 |
|a Orcutt, Jason Scott
|e contributor
|
100 |
1 |
0 |
|a Ram, Rajeev J.
|e contributor
|
700 |
1 |
0 |
|a Ram, Rajeev J.
|e author
|
245 |
0 |
0 |
|a Photonic Device Layout Within the Foundry CMOS Design Environment
|
260 |
|
|
|b Institute of Electrical and Electronics Engineers,
|c 2011-03-21T21:17:21Z.
|
856 |
|
|
|z Get fulltext
|u http://hdl.handle.net/1721.1/61756
|
520 |
|
|
|a A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
|
520 |
|
|
|a United States. Defense Advanced Research Projects Agency (DARPA)
|
520 |
|
|
|a National Science Foundation (U.S.)
|
546 |
|
|
|a en_US
|
655 |
7 |
|
|a Article
|
773 |
|
|
|t IEEE Photonics Technology Letters
|