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01291 am a22002413u 4500 |
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61756 |
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|a dc
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|a Orcutt, Jason Scott
|e author
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|a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
|e contributor
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|a Massachusetts Institute of Technology. Research Laboratory of Electronics
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|a Ram, Rajeev J.
|e contributor
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|a Orcutt, Jason Scott
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|a Ram, Rajeev J.
|e contributor
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|a Ram, Rajeev J.
|e author
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|a Photonic Device Layout Within the Foundry CMOS Design Environment
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|b Institute of Electrical and Electronics Engineers,
|c 2011-03-21T21:17:21Z.
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| 856 |
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|z Get fulltext
|u http://hdl.handle.net/1721.1/61756
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|a A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
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|a United States. Defense Advanced Research Projects Agency (DARPA)
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|a National Science Foundation (U.S.)
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|a en_US
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|a Article
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|t IEEE Photonics Technology Letters
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