An electrical-level superposed-edge approach to statistical serial link simulation
rute-force simulation approaches to estimating serial-link bit-error rates (BERs) become computationally intractable for the case when BERs are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans dozens of bit periods. Electrical-level statisti...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2012-07-27T18:31:13Z.
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| Subjects: | |
| Online Access: | Get fulltext |