Scalable, accurate multicore simulation in the 1000-core era

Scalable, accurate multicore simulation in the 1000-core era

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs bet...

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Bibliographic Details
Main Authors: Lis, Mieszko (Contributor), Ren, Pengju (Author), Cho, Myong Hyon (Contributor), Shim, Keun Sup (Contributor), Fletcher, Christopher Wardlaw (Contributor), Khan, Omer (Contributor), Devadas, Srinivas (Contributor)
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory (Contributor), Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers (IEEE), 2012-09-24T15:09:33Z.
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