Discrete-time, cyclostationary phase-locked loop model for jitter analysis
Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cy...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2012-10-18T20:55:33Z.
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| Subjects: | |
| Online Access: | Get fulltext |