Jigsaw: Scalable software-defined caches
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunatel...
| Main Authors: | , |
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| Other Authors: | , |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2014-10-09T13:41:29Z.
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| Subjects: | |
| Online Access: | Get fulltext |