Ion traps fabricated in a CMOS foundry

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-...

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Main Authors: Mehta, Karan Kartik (Contributor), Bruzewicz, Colin D. (Contributor), Sage, Jeremy M. (Contributor), Chiaverini, John (Contributor), Eltony, Amira (Author), Chuang, Isaac L. (Author), Ram, Rajeev J (Author)
Other Authors: Lincoln Laboratory (Contributor), Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor), Massachusetts Institute of Technology. Department of Physics (Contributor), Massachusetts Institute of Technology. Research Laboratory of Electronics (Contributor), MIT-Harvard Center for Ultracold Atoms (Contributor), Eltony, Amira M. (Contributor), Chuang, Isaac (Contributor), Ram, Rajeev J. (Contributor)
Format: Article
Language:English
Published: American Institute of Physics (AIP), 2015-11-13T17:37:45Z.
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