Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Desig...

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Bibliographic Details
Main Author: Bartholomew, David Ray
Format: Others
Published: BYU ScholarsArchive 2004
Subjects:
design
high speed
mixed-signal
CMOS
mutliplier
circuit
circuit design
short-channel
PMOS
transistors
MOSFET
Cadence Design Systems
nonlinearity
filtering
digital to analog conversion
linear equalization
short-channel effects
Electrical and Computer Engineering
Online Access:https://scholarsarchive.byu.edu/etd/126
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1125&context=etd

Internet

https://scholarsarchive.byu.edu/etd/126
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1125&context=etd

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