Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Desig...

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Main Author:	Bartholomew, David Ray
Format:	Others
Published:	BYU ScholarsArchive 2004
Subjects:	design high speed mixed-signal CMOS mutliplier circuit circuit design short-channel PMOS transistors MOSFET Cadence Design Systems nonlinearity filtering digital to analog conversion linear equalization short-channel effects Electrical and Computer Engineering
Online Access:	https://scholarsarchive.byu.edu/etd/126 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1125&context=etd

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spelling	ndltd-BGMYU2-oai-scholarsarchive.byu.edu-etd-11252021-09-12T05:00:50Z Design of a High Speed Mixed Signal CMOS Mutliplying Circuit Bartholomew, David Ray This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion. 2004-03-12T08:00:00Z text application/pdf https://scholarsarchive.byu.edu/etd/126 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1125&context=etd http://lib.byu.edu/about/copyright/ Theses and Dissertations BYU ScholarsArchive design high speed mixed-signal CMOS mutliplier circuit circuit design short-channel PMOS transistors MOSFET Cadence Design Systems nonlinearity filtering digital to analog conversion linear equalization short-channel effects Electrical and Computer Engineering
collection	NDLTD
format	Others
sources	NDLTD
topic	design high speed mixed-signal CMOS mutliplier circuit circuit design short-channel PMOS transistors MOSFET Cadence Design Systems nonlinearity filtering digital to analog conversion linear equalization short-channel effects Electrical and Computer Engineering
spellingShingle	design high speed mixed-signal CMOS mutliplier circuit circuit design short-channel PMOS transistors MOSFET Cadence Design Systems nonlinearity filtering digital to analog conversion linear equalization short-channel effects Electrical and Computer Engineering Bartholomew, David Ray Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
description	This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
author	Bartholomew, David Ray
author_facet	Bartholomew, David Ray
author_sort	Bartholomew, David Ray
title	Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
title_short	Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
title_full	Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
title_fullStr	Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
title_full_unstemmed	Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
title_sort	design of a high speed mixed signal cmos mutliplying circuit
publisher	BYU ScholarsArchive
publishDate	2004
url	https://scholarsarchive.byu.edu/etd/126 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1125&context=etd
work_keys_str_mv	AT bartholomewdavidray designofahighspeedmixedsignalcmosmutliplyingcircuit
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Design of a High Speed Mixed Signal CMOS Mutliplying Circuit

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