High Voltage Analog Design in a Standard Digital CMOS Process
This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a hig...
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| Format: | Others |
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BYU ScholarsArchive
2005
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| Online Access: | https://scholarsarchive.byu.edu/etd/809 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1808&context=etd |