High Voltage Analog Design in a Standard Digital CMOS Process
This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a hig...
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| Format: | Others |
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BYU ScholarsArchive
2005
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| Online Access: | https://scholarsarchive.byu.edu/etd/809 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1808&context=etd |
| Summary: | This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface. |
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