Circuit and Modeling Solutions for High-Speed Chip-to-Chip Communication
This dissertation presents methods for modeling and mitigating voltage noise and timing jitter across high-speed chip-to-chip interconnects. Channel equalization and associated tuning schemes have been developed to target the distinct characteristics and signal degradation exhibited in the clock and...
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| Format: | Others |
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BYU ScholarsArchive
2007
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| Online Access: | https://scholarsarchive.byu.edu/etd/1067 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2066&context=etd |