Reducing Power in FPGA Designs Through Glitch Reduction

Reducing Power in FPGA Designs Through Glitch Reduction

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to...

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Bibliographic Details
Main Author: Rollins, Nathaniel Hatley
Format: Others
Published: BYU ScholarsArchive 2007
Subjects:
FPGA
digital design
glitch reduction
power estimation
power reduction
RPower
JPower
XPower
activity-rate based power estimation
pipelining
retiming
energy area delay
energy metrics
probability model
transition model
Electrical and Computer Engineering
Online Access:https://scholarsarchive.byu.edu/etd/1105
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2104&context=etd

Internet

https://scholarsarchive.byu.edu/etd/1105
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=2104&context=etd

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