Using On-Chip Error Detection to Estimate FPGA Design Sensitivity to Configuration Upsets

Using On-Chip Error Detection to Estimate FPGA Design Sensitivity to Configuration Upsets

SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mi...

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Bibliographic Details
Main Author: Keller, Andrew Mark
Format: Others
Published: BYU ScholarsArchive 2017
Subjects:
FPGA
SEU mitigation
SEU sensitivity
reliability
error detection
triple modular
redundancy
TMR
duplication with compare
DWC
scrubbing
fault-tolerance
neutron radiation
testing
fault-injection
Electrical and Computer Engineering
Online Access:https://scholarsarchive.byu.edu/etd/6302
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=7302&context=etd

Internet

https://scholarsarchive.byu.edu/etd/6302
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=7302&context=etd

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