Time-multiplexed FPGA overlay networks on chip
How do we design a communication network for processing elements (PEs) on a single chip that minimizes application communication time and area? In designing such a network it is essential to use a network communication pattern that matches application communication and area requirements. This report...
| Main Author: | |
|---|---|
| Format: | Others |
| Published: |
2006
|
| Online Access: | https://thesis.library.caltech.edu/2335/1/final.pdf Mehta, Nikil (2006) Time-multiplexed FPGA overlay networks on chip. Master's thesis, California Institute of Technology. doi:10.7907/WZTS-XR26. https://resolver.caltech.edu/CaltechETD:etd-05312006-164103 <https://resolver.caltech.edu/CaltechETD:etd-05312006-164103> |
Internet
https://thesis.library.caltech.edu/2335/1/final.pdfMehta, Nikil (2006) Time-multiplexed FPGA overlay networks on chip. Master's thesis, California Institute of Technology. doi:10.7907/WZTS-XR26. https://resolver.caltech.edu/CaltechETD:etd-05312006-164103 <https://resolver.caltech.edu/CaltechETD:etd-05312006-164103>