Test and Debug Solutions for 3D-Stacked Integrated Circuits
<p>Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die...
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2015
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| Online Access: | http://hdl.handle.net/10161/10450 |