Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits
A high-performance 2D or 3D integrated circuit typically has (i) ratio of delay of a 1mm wire to delay of a nMOS transistor > 500, (ii) target impedence of power delivery network < 1mΩ, (iii) clock frequency > 2GHz, and (iv) thermal resistance requirement of heat removal path < 0.6 degr...
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Georgia Institute of Technology
2009
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| Online Access: | http://hdl.handle.net/1853/26562 |