Fatigue modeling of nano-structured chip-to-package interconnections
Driven by the need for increase in system¡¯s functionality and decrease in the feature size, International Technology Roadmap for Semi-conductors has predicted that integrated chip packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials that have be...
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Georgia Institute of Technology
2009
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| Online Access: | http://hdl.handle.net/1853/28263 |