Koh, S. W. (2009). Fatigue modeling of nano-structured chip-to-package interconnections. Georgia Institute of Technology.
Chicago Style (17th ed.) CitationKoh, Sau W. Fatigue Modeling of Nano-structured Chip-to-package Interconnections. Georgia Institute of Technology, 2009.
MLA (8th ed.) CitationKoh, Sau W. Fatigue Modeling of Nano-structured Chip-to-package Interconnections. Georgia Institute of Technology, 2009.
Warning: These citations may not always be 100% accurate.