Modeling, design, and characterization of through vias in silicon and glass interposers
Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integrat...
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Georgia Institute of Technology
2012
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| Online Access: | http://hdl.handle.net/1853/42737 |