Automated Bus Generation for Multi-processor SoC Design

Automated Bus Generation for Multi-processor SoC Design

In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effe...

Full description

Bibliographic Details
Main Author: Ryu, Kyeong Keol
Format: Others
Language:en_US
Published: Georgia Institute of Technology 2005
Subjects:
System-on-a-Chip (SoC)
Bus architecture
Design space exploration
Bus generation
Integrated circuits Very large scale integration Design and construction
Computer-aided design
Online Access:http://hdl.handle.net/1853/5076

Internet

http://hdl.handle.net/1853/5076

Similar Items