TCAD simulation framework for the study of TSV-device interaction
With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area re...
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Format: | Others |
Language: | en_US |
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Georgia Institute of Technology
2014
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Online Access: | http://hdl.handle.net/1853/51785 |