TCAD simulation framework for the study of TSV-device interaction
With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area re...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
Georgia Institute of Technology
2014
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1853/51785 |