Built-in test for performance characterization and calibration of phase-locked loops
The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Diff...
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ndltd-GATECH-oai-smartech.gatech.edu-1853-517902014-09-25T03:34:12ZBuilt-in test for performance characterization and calibration of phase-locked loopsHsiao, Sen-WenPhase-locked loopBuilt-in testBuilt-in self-testCalibrationAnalog sensorReference spurFrequency synthesizersTelecommunication systemsPhase detectorsPhase-locked loopsThe objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.Georgia Institute of TechnologyChatterjee, Abhijit2014-05-22T15:20:56Z2014-05-22T15:20:56Z2014-052014-01-07May 20142014-05-22T15:20:56ZDissertationapplication/pdfhttp://hdl.handle.net/1853/51790en_US |
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Phase-locked loop Built-in test Built-in self-test Calibration Analog sensor Reference spur Frequency synthesizers Telecommunication systems Phase detectors Phase-locked loops |
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Phase-locked loop Built-in test Built-in self-test Calibration Analog sensor Reference spur Frequency synthesizers Telecommunication systems Phase detectors Phase-locked loops Hsiao, Sen-Wen Built-in test for performance characterization and calibration of phase-locked loops |
description |
The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system. |
author2 |
Chatterjee, Abhijit |
author_facet |
Chatterjee, Abhijit Hsiao, Sen-Wen |
author |
Hsiao, Sen-Wen |
author_sort |
Hsiao, Sen-Wen |
title |
Built-in test for performance characterization and calibration of phase-locked loops |
title_short |
Built-in test for performance characterization and calibration of phase-locked loops |
title_full |
Built-in test for performance characterization and calibration of phase-locked loops |
title_fullStr |
Built-in test for performance characterization and calibration of phase-locked loops |
title_full_unstemmed |
Built-in test for performance characterization and calibration of phase-locked loops |
title_sort |
built-in test for performance characterization and calibration of phase-locked loops |
publisher |
Georgia Institute of Technology |
publishDate |
2014 |
url |
http://hdl.handle.net/1853/51790 |
work_keys_str_mv |
AT hsiaosenwen builtintestforperformancecharacterizationandcalibrationofphaselockedloops |
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1716714475498766336 |