Cache design and timing analysis for preemptive multi-tasking real-time uniprocessor systems
In this thesis, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task in a preemptive multi-tasking single-processor real-time system utilizing an L1 cache. The approach combines inter-task cache eviction analysis and intra-task cache access analysis to estimate the Cac...
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Format: | Others |
Language: | en_US |
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Georgia Institute of Technology
2005
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Online Access: | http://hdl.handle.net/1853/6919 |