Cache design and timing analysis for preemptive multi-tasking real-time uniprocessor systems

Cache design and timing analysis for preemptive multi-tasking real-time uniprocessor systems

In this thesis, we propose an approach to estimate the Worst Case Response Time (WCRT) of each task in a preemptive multi-tasking single-processor real-time system utilizing an L1 cache. The approach combines inter-task cache eviction analysis and intra-task cache access analysis to estimate the Cac...

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Bibliographic Details
Main Author: Tan, Yudong
Format: Others
Language:en_US
Published: Georgia Institute of Technology 2005
Subjects:
Real-time systems
Multi-tasking
Cache
Timing analysis
Real-time data processing
Cache memory
Memory management (Computer science)
Online Access:http://hdl.handle.net/1853/6919

Internet

http://hdl.handle.net/1853/6919

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