Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration
The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line....
Main Author: | |
---|---|
Format: | Others |
Language: | en_US |
Published: |
Georgia Institute of Technology
2006
|
Subjects: | |
Online Access: | http://hdl.handle.net/1853/7503 |