Uma metodologia para identificação de módulos de circuitos integrados propensos a erros
=== Verifying large industrial designs is getting harder each day. The current verification methodologies can not guarantee bug free designs. Considering that is not possible to check all states of complex designs, the verification team should define coverage levels for each integrated circuit modu...
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| Format: | Others |
| Language: | English |
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Universidade Federal de Minas Gerais
2011
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| Online Access: | http://hdl.handle.net/1843/SLSS-8GYG2K |