The development of a hardware abstraction layer generator for system-on-chip functional verification

The development of a hardware abstraction layer generator for system-on-chip functional verification

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Bibliographic Details
Main Author: Sampaio Lins, Tiago
Other Authors: Natividade da Silva Barros, Edna
Language:Portuguese
Published: Universidade Federal de Pernambuco 2014
Subjects:
Microeletrônica
Circuitos semicondutores
Online Access:https://repositorio.ufpe.br/handle/123456789/2452

Internet

https://repositorio.ufpe.br/handle/123456789/2452

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