Metodologia de Verifica??o Funcional para Circuitos Anal?gicos

Metodologia de Verifica??o Funcional para Circuitos Anal?gicos

Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 AdautoLT.pdf: 2061017 bytes, checksum: 12a139ba25174e3b22d08cf31c934500 (MD5) Previous issue date: 2009-09-04 === Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior === This work proposes a new methodology to ver...

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Bibliographic Details
Main Author: Fonseca, Adauto Luis Tadeo Bernardes da
Other Authors: CPF:88464911491
Format: Others
Language:Portuguese
Published: Universidade Federal do Rio Grande do Norte 2014
Subjects:
Verifica??o
Circuitos anal?gicos
T?cnicas de verifica??o
Ambiente de Verifica??o
VHDL-AMS
Verification
Analog circuits
Integrated circuits
Verification techniques
Verification environment
CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
Online Access:http://repositorio.ufrn.br:8080/jspui/handle/123456789/15298

Internet

http://repositorio.ufrn.br:8080/jspui/handle/123456789/15298

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