Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplica??es gen?ricas utilizando redes neurais artificiais embarcadas
Made available in DSpace on 2014-12-17T14:55:47Z (GMT). No. of bitstreams: 1 RafaelNAP_DISSERT.pdf: 1349793 bytes, checksum: 6843077c7952b1e58788ef395d9822e6 (MD5) Previous issue date: 2011-02-22 === This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural...
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Format: | Others |
Language: | Portuguese |
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Universidade Federal do Rio Grande do Norte
2014
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Online Access: | http://repositorio.ufrn.br:8080/jspui/handle/123456789/15342 |