Modelagem e valida??o de redes intrachip atrav?s de s?ntese comportamental
Made available in DSpace on 2015-04-14T14:48:59Z (GMT). No. of bitstreams: 1 402108.pdf: 3755135 bytes, checksum: 7d348d529638f63dbd140311e4213857 (MD5) Previous issue date: 2007-10-31 === A crescente demanda pela redu??o do time-to-market para SoCs (System-on-chip) leva a mudan?as essenciais na m...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | Portuguese |
| Published: |
Pontif?cia Universidade Cat?lica do Rio Grande do Sul
2015
|
| Subjects: | |
| Online Access: | http://tede2.pucrs.br/tede2/handle/tede/5021 |