Técnicas de tolerância a falhas aplicadas a redes intra-chip
Made available in DSpace on 2015-06-17T02:04:12Z (GMT). No. of bitstreams: 1 000470587-Texto+Completo-0.pdf: 6163395 bytes, checksum: b88f0389d39c7cc7f197b32966e6fe29 (MD5) Previous issue date: 2015 === The continuous development of the transistor technology has enabled hundreds of processors to w...
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| Language: | Portuguese |
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Pontifícia Universidade Católica do Rio Grande do Sul
2015
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| Online Access: | http://hdl.handle.net/10923/7393 |