Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector

Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the numbe...

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Bibliographic Details
Main Author: Raghavendra, R G
Other Authors: Amrutur, Bharadwaj
Language:en_US
Published: 2011
Subjects:
Special Devices (Computer Engineering)
Analog Frequency Detector
Charge Pump Phase Locked Loop
Phase Locked Loop (PLL)
Phase Locked Loop Filters
Phase Locked Loop Filter Design
Summer-Less Dual Charge Pump Based Loop Filters
Loop Filter Design
Computer Engineering
Online Access:http://hdl.handle.net/2005/1006

Internet

http://hdl.handle.net/2005/1006

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