Power Efficient Last Level Cache for Chip Multiprocessors

Power Efficient Last Level Cache for Chip Multiprocessors

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The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip cache has become very significant. We explore various techniques to switch-off the over-allocated cache so as to reduce leakage power consumed...

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Bibliographic Details
Main Author: Mandke, Aparna
Other Authors: Srikant, Y N
Language:en_US
Published: 2017
Subjects:
Processor Architecture
Chip Multiprocessor
Cache Memory
Cache
Genetic Algorithms
Leakage Power Optimization
Working Set Size Optimization
Near Optimal Remap Configuration
Thread Contention Predictors
On-Chip Cache
Cache Architecture
NUCA
SNUCA
Non-Uniform Cache Architecture
Computer Science
Online Access:http://etd.iisc.ernet.in/handle/2005/2802
http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf

Internet

http://etd.iisc.ernet.in/handle/2005/2802
http://etd.ncsi.iisc.ernet.in/abstracts/3574/G25417-Abs.pdf

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