Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques

Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques

Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level parallelism in architectures such as very Long Instruction Word and tiled processor...

Full description

Bibliographic Details
Main Author: Nagarakatte, Santosh G
Other Authors: Govindarajan, R
Language:en_US
Published: 2009
Subjects:
Compilers
Parallel Processing
Instruction Scheduling
Software Pipelining
Spill Code Scheduling
Stream Programs - Scheduling
Genetic Algorithms
Integer Linear Programming
Software Pipelined Loops
Register Allocation
Computer Science
Online Access:http://hdl.handle.net/2005/507

Internet

http://hdl.handle.net/2005/507

Similar Items