Efficient Compilation Of Stream Programs Onto Multi-cores With Accelerators
Over the past two decades, microprocessor manufacturers have typically relied on wider issue widths and deeper pipelines to obtain performance improvements for single threaded applications. However, in the recent years, with power dissipation and wire delays becoming primary design constraints, this...
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| Language: | en_US |
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2010
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| Online Access: | http://hdl.handle.net/2005/971 |