Period and glitch reduction via clock skew scheduling, delay padding and glitchless
This thesis describes PGR, an architectural technique to reduce dynamic power via a glitch reduction strategy named GlitchLess, or to improve performance via clock skew scheduling (CSS) and delay padding (DP). It is integrated into VPR 5.0, and is invoked after the routing stage. Programmable delay...
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| Format: | Others |
| Language: | English |
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University of British Columbia
2009
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| Online Access: | http://hdl.handle.net/2429/12869 |