Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters
Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use to...
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| Format: | Others |
| Language: | English |
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University of British Columbia
2008
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| Online Access: | http://hdl.handle.net/2429/1447 |