A combined clustering and placement algorithm for FPGAs
One of the major drawbacks of reprogrammable microchips, such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of are...
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| Format: | Others |
| Language: | en |
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University of British Columbia
2007
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| Online Access: | http://hdl.handle.net/2429/209 |