A hybrid phase-locked loop for clock and data recovery applications
Clock and data recovery (CDR) circuits are among critical building blocks of wireline receivers. In these receivers, typically after compensating for the adverse effects of the channel by an equalizer, the received signal is processed to the CDR block. The timing of the signal is first extracted (cl...
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| Language: | English |
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University of British Columbia
2010
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| Online Access: | http://hdl.handle.net/2429/27486 |