A hybrid phase-locked loop for clock and data recovery applications

• Main Author: Jalali, Mohammad Sadegh
• Language: English
• Published: University of British Columbia 2010
• Online Access: http://hdl.handle.net/2429/27486

Clock and data recovery (CDR) circuits are among critical building blocks of wireline receivers. In these receivers, typically after compensating for the adverse effects of the channel by an equalizer, the received signal is processed to the CDR block. The timing of the signal is first extracted (clock recovery), and then the actual data is recovered (data recovery). To recover the clock, phase-locked loops (PLLs) are usually used. The PLL output can track the phase and the frequency of its input. In this thesis, a hybrid PLL architecture is proposed. The PLL starts its operation using a binary phase/frequency detector (PFD) to achieve a fast lock and a wide tuning range. The operation is then automatically switched to a linear phase detector (PD) to achieve a low jitter clock signal upon lock, and finally the bandwidth is decreased to decrease the output jitter even more. Automatic switching of the operation from the binary to the linear PD is achieved by detecting the point at which the clock frequency crosses the data frequency. This PLL structure is particularly suitable for CDR applications, as its output is insensitive to continuous data streams. Also, a feedback-based technique is used in the charge pump (CP) to increase its swing. This is done by detecting the change in the drain-source voltages of the current source transistors of the CP and changing their gate-source voltages in a closed-loop feedback system to keep their currents constant. The PLL is designed and simulated in a 0.13 μm CMOS technology. Post-layout simulations show that the tuning range of the PLL is from ∼8.3 GHz to 9.6 GHz, and it consumes about 35 mW from a 1.2 V supply and has a deterministic jitter of about 35 fs. The total random jitter of the designed PLL is about 0.1 unit interval (UI) (11.7 ps with a clock frequency of 8.5 GHz). The worst-case lock time of the PLL is slightly less than 30 ns.