Reliable high-throughput FPGA interconnect using source-synchronous surfing and wave pipelining
FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial...
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| Language: | English |
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University of British Columbia
2008
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| Online Access: | http://hdl.handle.net/2429/2767 |