A VHDL front end
VHDL (the VHSIC Hardware Description Language) is an industry standard language used to describe hardware from the rather abstract behaviors to the very concrete circuits. This thesis is about the design and implementation of a VHDL front end. A brief introduction to VHDL is given with easy-to-un...
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| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/2429/3438 |