On-chip Power Grid Verification with Reduced Order Modeling
To ensure the robustness of an integrated circuit design, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has...
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| Language: | en_ca |
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2010
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| Online Access: | http://hdl.handle.net/1807/25602 |