Digital Timing Control in SRAMs for Yield Enhancement and Graceful Aging Degradation
Embedded SRAMs can occupy the majority of the chip area in SOCs. The increase in process variation and aging degradation due to technology scaling can severely compromise the integrity of SRAM memory cells, hence resulting in cell failures. Enough cell failures in a memory can lead to it being rejec...
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| Language: | en |
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2010
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| Online Access: | http://hdl.handle.net/10012/5355 |