A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters

A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timi...

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Bibliographic Details
Main Author: Bray, Adam
Language:en
Published: 2013
Subjects:
ADC
Analog to Digital Converter
Converters
Jitter
Timing Skew
Interleaved
TI-ADC
Time Interleaved
Analog
Online Access:http://hdl.handle.net/10012/8053

Internet

http://hdl.handle.net/10012/8053

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