Worst Case Analysis of DRAM Latency in Hard Real Time Systems
As multi-core systems are becoming more popular in real time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predicta...
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| Language: | en |
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2013
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| Online Access: | http://hdl.handle.net/10012/8099 |