On low power floating point data path architectures

On low power floating point data path architectures

This work targets development of higher level design methodologies for the implementation of low power floating point units--adders, multipliers and multiply-accumulators. Philosophically, higher level design starts with the characterization of the behavior of the system under consideration. In this...

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Bibliographic Details
Main Author: Pillai, Rajan V. K
Format: Others
Published: 1999
Online Access:http://spectrum.library.concordia.ca/955/1/NQ47712.pdf
Pillai, Rajan V. K <http://spectrum.library.concordia.ca/view/creators/Pillai=3ARajan_V=2E_K=3A=3A.html> (1999) On low power floating point data path architectures. PhD thesis, Concordia University.

Internet

http://spectrum.library.concordia.ca/955/1/NQ47712.pdf
Pillai, Rajan V. K <http://spectrum.library.concordia.ca/view/creators/Pillai=3ARajan_V=2E_K=3A=3A.html> (1999) On low power floating point data path architectures. PhD thesis, Concordia University.

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